The invention relates to a charge-coupled image sensor arrangement of the line transfer type comprising a semiconductor body which is provided at a surface with a system of adjacent parallel n-phase charge-coupled devices. Each charge-coupled device forms a line of a bidimensional pattern of photosensitive elements (pixels), in which incident radiation of a radiation image can be converted into a charge packet, whose size is determined by the intensity of the incident radiation. These charge-coupled devices comprise an n-phase clock electrode system having electrodes which alternately belong to one of the said phases, while the electrodes of a first of the said n phases for each charge-coupled device can be controlled selectively and the electrodes of the remaining (n-1) phases are common to the whole system. As a result, when a suitable voltage is applied to the electrodes of the first phase of a selected charge-coupled device, a selected line of the bidimensional pattern can be read. The charge packets of the unselected lines are permanently stored in the corresponding charge-coupled devices.
The charge-coupled devices can be of the known surface channel type or buried channel type. The device can further be a usual two-, three- or four-phase system.
Such image sensor arrangements are known, for example, from U.S. Pat. No. 4,242,700. In these arrangements, the image recorded and converted into a charge packet is read line-sequentially by clocking selectively the relevant charge-coupled device. After reading, this charge-coupled device is ready again, if desired, for again recording a line of the image, while at the same time the remaining lines are read. In contrast with more usual charge-coupled image sensor arrangements of the frame transfer type or interline type, in which the generated charge pattern is temporarily stored in a memory before being read, a sensor arrangement of the line transfer type does not require a separate memory. This means either that the whole surface area of the chip can be smaller than in frame transfer arrangements or interline arrangements or that with unchanged surface area the photosensitive part of the whole chip surface area can be comparatively larger.
The aforementioned U.S. Patent discloses with reference to FIG. 4 and the following Figures a two-phase embodiment, in which a fixed voltage is applied to the common electrodes and in which an alternating voltage, which is alternately higher and lower than the said fixed voltage, is applied to the electrodes of the first phase of a selected line. This voltage is chosen so that generated charge carriers are stored in potential wells below the common electrodes defining the centre of the pixels. The electrode configuration is such that the pixels in adjacent lines are shifted by a half pitch with respect to each other. When reading the matrix, each time two successive lines are read in time division multiplex. Thus, per line a quasi doubling and hence also a considerable improvement in resolution is obtained.
This improvement can be attained by the specific configuration of the common electrodes. Also in embodiments with other electrode configurations, in which, for example, in the column direction the common electrodes are constituted by straight strips defining in the subjacent charge transport channels columns of charge storage sites, a high resolution is often desirable. In the device described above having relatively offset electrodes, it may also be of importance to increase the resolution to an even higher level.